Modern electronic circuits are often designed and subsequently manufactured using software tools, commonly referred to as electronic design automation (EDA) tools. For example, a circuit designer will define the intended functionality of the circuit (e.g., using a hardware description language), and the EDA tools translate the intended functionality to a layout of logic gates and/or hardware components that achieve the intended functionality. When generating the layout, the EDA tools account for design rules provided by a foundry or semiconductor manufacturer that the circuit designer has chosen to fabricate the circuit. The design rules may specify various restrictions or limitations on feature geometry, spacing, and the like, for the various layers of the circuit that account for fabrication process variations for the particular technology node that the circuit is to be fabricated in. By ensuring that the layout satisfies the design rules provided by the foundry, the circuit designer is assured that the circuit can be fabricated in the desired technology node with a sufficient yield.
In some situations, a circuit designer may desire that one or more of the design rules provided by the foundry be relaxed to achieve desired performance targets or other objectives. However, in practice, the number and complexity of the design rules increases at smaller technology nodes. Thus, it is increasingly difficult for circuit designers to assess the impact of individual design rules on a layout and identify how relaxing particular design rules would affect the performance and/or yield of the fabricated device. Accordingly, it is desirable to provide a means for analyzing the impact of design rules on a layout.